1. Field of the Invention
The present invention relates to a method of fabricating nonvolatile memory devices and, more particularly, to a method of fabricating nonvolatile memory devices which embody a NOR flash cell with a stacked oxide layer with 4F2 unit cell area.
2. Background of the Related Art
In general, there are two categories in semiconductor devices, namely, volatile memory and non-volatile memory. Volatile memory includes dynamic random access memory (hereinafter referred to as “DRAM”) and static DRAM (hereinafter referred to as “SDRAM”). One characteristic of volatile memory is that data is maintained only while electric power is applied. In other words, when power is turned off, the data in the volatile memory disappears. On the other hand, non-volatile memory, mainly ROM (Read Only Memory), can maintain data regardless of the application of electric power.
From the point of a view of a fabrication process, non-volatile memory is divided into a floating gate type and a metal insulator semiconductor (hereinafter referred to as “MIS”) type. The MIS type has doubly or triply deposited dielectric layers which comprise at least two kinds of dielectric materials.
The floating gate type stores data using potential wells, and is represented by an ETOX (Electrically erasable programmable read only memory Tunnel OXide) used in a flash EEPROM (Electrically Erasable Programmable Read Only Memory).
The MIS type performs program operation using traps at a bulk dielectric layer, an interface between dielectric layers, and an interface between a dielectric layer and a semiconductor. Metal/Silicon ONO Semiconductor (hereinafter referred to as “MONOS/SONOS”) structure mainly used for the flash EEPROM is a representative MIS structure.
Referring to FIG. 1, a device isolation structure 11 is formed on a semiconductor substrate 10, on which a gate oxide layer 12 is formed. A first polysilicon layer 13 formed on the gate oxide layer 12 is then used as a floating gate. A dielectric layer 15 and a second polysilicon layer 16 are sequentially formed on the floating gate 13, and the second polysilicon layer 16 is used as a control gate. A flash memory cell is then completed by depositing a metal layer 17 and a nitride layer 18 on the control gate 16, and by patterning them in cell structure.
For the present fabricating processes of NOR flash memories, a self-aligned source (hereinafter referred to as “SAS”) process or a self-aligned shallow trench isolation (hereinafter referred to as “SA-STI”) process is chiefly adopted to minimize the unit cell area of the NOR flash memories. Although the SAS or the SA-STI processes or even both processes are applied, the unit cell area can not be reduced down to the minimum area(4F2) of a NAND flash cell, because a bit contact must be formed.